The present invention relates to a semiconductor device and its manufacturing method and in particular to a semiconductor device having substantially the same size as a semiconductor chip when viewed from above and where the semiconductor chip and a wiring pattern are electrically connected to each other and its manufacturing method.
In recent years, semiconductor application products have been rapidly downsized, thinned and reduced in weight for applications in a variety of mobile devices such as digital cameras and cell phones. With this trend, semiconductor devices such as NAND-type flash memories have been requested to shrink and to support higher packing density. A semiconductor device (refer to FIG. 1) has been proposed that is called CSP (Chip Size Package) having substantially the same size as a semiconductor chip viewed from above.
FIG. 1 is a cross-sectional view of a related art semiconductor device.
As shown in FIG. 1, a related art semiconductor device 100 includes a semiconductor chip 101, an internal connection terminal 102, a resin layer 103, a wiring pattern 104, a solder resist 106, and an external connection terminal 107.
The semiconductor chip 101 includes a semiconductor substrate 110 reduced in thickness, a semiconductor integrated circuit 111, a plurality of electrode pads 112, and a protective film 113. The semiconductor integrated circuit 111 is arranged on the front surface of the semiconductor substrate 110. The semiconductor integrated circuit 111 includes a diffusion layer, an insulation layer, vias, wiring and the like. The plurality of electrode pads 112 are arranged on the semiconductor integrated circuit 111. The plurality of electrode pads 112 are electrically connected to the wiring arranged on the semiconductor integrated circuit 111. The protective film 113 is arranged on semiconductor integrated circuit 111. The protective film 113 is a film used to protect the semiconductor integrated circuit 111.
The internal connection terminal 102 is arranged on the electrode pad 112. The upper surface 102A of the internal connection terminal 102 is exposed from the resin layer. An upper surface of the internal connection terminal 102 is connected to the wiring pattern 104. The resin layer 103 is arranged to cover the side of the semiconductor substrate 101 where the internal connection terminal 102 is arranged.
The wiring pattern 104 is arranged on the resin layer 103. The wiring pattern 104 is connected to the internal connection terminal 102. The wiring pattern 104 is electrically connected to the electrode pads 112 via the internal connection terminal 102. The wiring pattern 104 has an external connection terminal arrangement region 104A where the external connection terminal 107 is arranged. The solder resist 106 is arranged on the upper surface 103A of the resin layer 103 to cover the portion of the wiring pattern 104 except the external connection terminal arrangement region 104A.
FIGS. 2 to 10 show the manufacturing process of a related art semiconductor device. In FIGS. 2 to 10, the same sign is given to the same component as that of the related art semiconductor device 100.
The method for manufacturing the related art semiconductor device 100 will be described referring to FIGS. 2 to 10. In the process shown in FIG. 2, the semiconductor chip 101 including the semiconductor integrated circuit 111, the plurality of electrode pads 112 and the protective film 113 is formed on the front surface of the semiconductor substrate 110 before being reduced in thickness. Next, in the process shown in FIG. 3, the internal connected terminals 102 are formed on the plurality of electrode pads 112. In this stage, there are variations in height between the plurality of internal connected terminals 102.
Next, in the process shown in FIG. 4, the resin layer 103 in a semi-cured state is formed to cover the plurality of internal connection terminals 102 and the upper surface 113A of the protective film 113. In the process shown in FIG. 5, a metallic layer 115 is formed to cover the upper surface 103A of the resin layer 103. The metallic layer 115 is a layer that serves as the matrix of the wiring pattern 104.
Next, in the process shown in FIG. 6, the metallic layer 115 and the plurality of internal connection terminals 102 are press-fitted to each other and the resin layer 103 in the semi-cured state is cured by pressing the metallic layer 115 with a structure shown in FIG. 5 heated. It is thus possible to electrically connect the metallic layer 115 and the plurality of internal connection terminals 102 even in the presence of variations in height between the plurality of internal connection terminals 102.
Next, in the process shown in FIG. 7, the metallic layer 115 shown in FIG. 6 is patterned to form the wiring pattern 104. Next, in the process shown in FIG. 8, the solder resist 106 is formed to cover the portion of the wiring pattern 104 except the external connection terminal arrangement region 104A and the upper surface 103A of the resin layer 103. The solder resist 106 is used to protect the wiring pattern 104.
Next, in the process shown in FIG. 9, the semiconductor substrate 110 is polished from the rear side of the semiconductor substrate 110 to thin the semiconductor substrate 110. Next, in the process shown in FIG. 10, the external connection terminal 107 is formed in the external connection terminal arrangement region 104A. The semiconductor device 100 is manufactured from these processes (for example, refer to Patent Reference 1).
[Patent Reference 1] JP-A-2008-84958
FIG. 11 is a plan view of a related art semiconductor device. In FIG. 11, the same sign is given to the same component as that of the related art semiconductor device 100. In FIG. 11, the external connection terminal 107 is not shown for simplicity.
In the related art semiconductor device 100, the solder resist 106 is arranged only on a main surface of the semiconductor device 100 to cover the entire upper surface 103A of the portion of the insulation layer 103 not corresponding to the forming region of the wiring pattern 104. This results in warpage of the semiconductor device 100.
Another problem is that difference in the thermal expansion coefficient between the solder resist 106 and the semiconductor substrate 110 leads to warpage of the semiconductor device 100.